1. Field of the Invention
The present invention relates to a semiconductor switching apparatus used for e.g., a power converter, and to a method of controlling a semiconductor switching element.
2. Description of the Background Art
FIG. 16 is a diagram showing an example of a circuit configuration of a prior-art semiconductor switching apparatus. In FIG. 16, a semiconductor switching apparatus is given reference character 3P, which is herein a GTO (Gate Turn-off Thyristor). A gate driver 4P connected between the gate and cathode of GTO 3P produces a gate turn-on control current IGP and applies the current IGP to the gate of GTO 3P to turn the GTO 3P on. Further, the driver 4P conducts a gate reverse current IGQP whose rate of rise of current (dIDQP/dt) is in a range of 20 to 50 A/μs from the gate to the cathode of GTO 3P. The gate reverse current Igqp is separated from the anode current IAP. At this time, a turn-off gain ranges from 2 to 5, and the GTO 3P is turned off.
To suppress the rate of rise of voltage (dVAKP/dt) and peak value of the anode-cathode voltage VAKP, a snubber circuit is generally used. The snubber circuit herein has a configuration where a snubber capacitor CS and a snubber diode DS are connected in parallel to the GTO 3P, and a snubber resistor RS is connected in parallel to the snubber diode DS in order to discharge the electric charges accumulated in the snubber capacitor CS at a turn-off.
An inductance 1P suppresses the rate of rise of anode current (dIAP/dt) which flows when the GTO 3P is turned on to not more than 1000 A/μs, and a circulating diode 2P connected in parallel to the inductance 1P circulates energy generated in the inductance 1P when the GTO 3P is turned off.
Furthermore, an inductance LS is a total inductance of the snubber circuit.
FIG. 17 shows observed waveforms in a turn-off test of the circuits in semiconductor switching apparatus. In FIG. 17, the waveforms C1P, C2P and C3P represent the anode current IAP, the anode-cathode voltage VAKP and the gate reverse current IGQP, respectively, and the horizontal axis indicates time.
In FIG. 17, at time tP1, the GTO 3P is in a turn-off state, and the gate reverse current IGQP is 0. At this time, the gate reverse current IGQP is increased, with the the rate of rise of the gate reverse current (dIGQP/dt) ranging from 20 to 50 A/μs. When the gate reverse current reaches the peak value, the anode current IAP starts falling and the anode-cathode voltage VAKP of the GTO 3P starts rising. At the same time, a current IS starts flowing towards the above-discussed snubber circuit side, and a voltage is developed by the rate of rise of the current Is and the inductance LS in the snubber circuit (snubber inductance) and the capacitor's charge voltage by the current IS, and is then superimposed on the anode-cathode voltage VAKP to generate a spike voltage VDSP at time tP3. The spike voltage VDSP is likely to cause a dissipation. For example, a current flow of about 4000 A brings the dissipation of as much as several MW. Therefore, it is required to suppress the spike voltage VDSP to as low as possible and continued efforts to reduce the snubber inductance LS have been made.
The rate of rise of the anode-cathode voltage (dVAKP/dt) constantly changes after the spike voltage VDSP is generated. The anode current IAP continues to flow after time dP3 and this is referred to as a “tail current”. The tail current reaches the maximum at time tP4. The tail current and the anode-cathode voltage VAKP produce further power dissipation. The anode-cathode voltage VAKP reaches a peak voltage at time tP5. After that, the anode-cathode voltage VAKP reaches a power voltage (or main line voltage) VDD.
To suppress the rate of rise of voltage (dVAKP/dt), the above-discussed snubber capacitor CS is required. The snubber capacitor CS has a capacitance value IAP/(dVAKP/dt) which is generally selected so as to satisfy the relation dVAKP/dt≦f 1000 V/μs (the dVAKP/dt is calculated by the following equation: dVAKP/dt≈IAP/CS).
FIGS. 18 and 19 illustrate a configuration of the background-art GTO 3P (consisting of a GTO element package and two stacked electrodes) used in the semiconductor switching apparatus of FIG. 16, inclusive of the gate driver 4P. FIG. 18 is a side view of the GTP 3P viewed from the direction of the arrow DP2 of FIG. 19, and partly a sectional view. FIG. 19 is a plan view of the GTO 3P exclusive of a stacked electrode 27Pa viewed from the direction of the arrow DP1 of FIG. 18.
FIGS., 18 and 19 show a GTO element (or GTO device) 20P, an internal inductance 4PL of the gate driver 4P, an external gate lead (gate drawing line) 21P and an external cathode lead (cathode drawing line) 22P both of which are formed of coaxial shield leads or twisted lead lines. A gate terminal 25P of the GTO element 20P and an end of the external gate lead 21P are joined to a metal joining member (or terminal) 23P by soldering to be fixed with each other. Similarly, a cathode terminal 26P of the GTO element 20P and an end of the external cathode lead 22P are joined to a metal joining member 24P by soldering to be fixed with each other. Thus, both the terminals 25P and 26P are connected to the gate driver 4P through the leads 21P and 22P, respectively.
Stacked electrodes 27Pa and 27Pb apply pressure onto the GTO element 20P.
A semiconductor substrate (or wafer) 28P is provided with segments of the GTO, a gate electrode 29Pa made of Al (Aluminum) is formed on an outermost peripheral portion of an upper surface of the semiconductor substrate 28P, and a cathode electrode 29Pb is formed inside the gate electrode 29Pa on the upper surface, correspondingly to the segment. A cathode strain relieving plate (or metal plate) 30P and a cathode post electrode 31P are stacked in this order on an upper surface of the cathode electrode 29Pb provided on the upper surface of the semiconductor substrate 28P. An anode strain relieving plate 32P and an anode post electrode 33P are stacked in this order on a surface of an anode electrode (not shown) provided on a bottom surface of the semiconductor substrate 28P (opposite to the cathode electrode 29Pb).
A ring-shaped gate electrode 34P is in contact with an upper surface of the gate electrode 29Pa on the semiconductor substrate 28P, and a belleville spring 35P pushes the ring-shaped gate electrode 34P against the gate electrode 29Pa through an annular insulator 36P. An insulating sheet 37P is provided to isolate the ring-shaped gate electrode 34P from the cathode strain relieving plate 30P and the post electrode 31P. A gate lead 38P has one end which is fitted into the ring-shaped gate electrode 34P by brazing or welding and the other end which is electrically connected to the gate terminal 25P. A first flange 39P has one end which is fitted into the cathode post electrode 31P and the other end which serves as a cathode terminal 26P, and a second flange 40P has one end which is fitted into the anode post electrode 33P. An insulating tube (or ceramic) 41P has an opening whose internal surface is provided with the gate terminal 25P, and a projection 42P. End portions 43Pa and 43Pb of the insulating tube 41P are protruded through its upper and lower surfaces to be fitted airtightly to the first and second flanges 39P and 40P respectively, thereby ensuring a closed structure of the GTO element 20P.
The above-discussed background-art semiconductor switching apparatus has the following two problems.
(1) As shown in FIG. 19, the external gate lead 21P which draws the gate reverse current is taken out from a localized portion inside the ring-shaped gate electrode 34P. Accordingly, only one-way drawing of the gate reverse current is made. As a result, when the GTO is turned off, with nonuniform cathode current, the loss produced by the spike voltage and the tail current, i.e., dissipation, is locally concentrated on the cathode side surface inside the GTO, the GTO device is failed by a local rise of temperature, to fall into a conductive state. Thus, there arises a problem that failure of the turn-off occurs with high probability.
FIGS. 20 and 21 are a plan view and a sectional view of the GTO element, respectively, which schematically illustrate the above problem in the background art. FIG. 21 is a part of the sectional view taken along the line CSA-CSB of FIG. 20. Specifically discussing, the gate reverse current of the GTO segment formed on a region in the vicinity of the ring-shaped gate electrode 34P, such as a region REO, is drawn earlier than that of the GTO segment formed in a region REI, further inside the region REO within a cylindrical wafer, and therefore the GTO segment in the region REO are turned off earlier. In contrast, the GTO segment formed in the region REC of the wafer takes the longest turn-off time, and a cathode current IK flows towards the cathode electrodes of the GTO segments in the central region REC from the GTO segments in the regions around the region REC to cause a current crowding in a localized portion inside the wafer of the GTO.
(2) The second problem is caused by the snubber circuit, in particular, the snubber capacitor. Specifically discussing, the electric charges which are charged up in the snubber capacitor CS (see FIG. 16) at a turn-off have to be completely discharged until the next turn-off, and therefore the charges of the snubber capacitor are discharged through the snubber resistor RS when the GTO 3P is turned on, to thereby cause dissipation of large amount. At this time, the capacitance of power consumption in the snubber resistor RS is expressed as PW=½×CS×f(VDD2+(VDM−VDD)2), where VDD and VDM represent the power supply voltage and a voltage of the snubber capacitor CS which is charged up at the turn-off, respectively. For this reason, a cooling device is required for cooling the whole apparatus.
Thus, when the GTO 3P is connected to the snubber resistor which has the above capacitance of power consumption, the power generated by the snubber resistor is out of the power to be transmitted as a loss to degrade the efficiency, and further the necessity for the cooling device arises. That is a hindrance to simplification and size-reduction of the whole apparatus.